Timing Analysis of a D-PET Fip-flop Component

Abstract

The preset and clear input are active-low, because there are an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.When the preset input is activated, the flip-flop will be reset (Q=0, not-Q=1) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be set (Q=1, not-Q=0), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are not activated ( both of them 0 ) ? Surprise, surprise: we get an invalid state on the output, where Q and not-Q go to the same state. when both preset and clear inputs are activated then the flip flop will work normally Diagram 2. The flip flop is a basic building block of sequential logic circuits.

 It is a circuit that has two stable states and can store one bit of state information.

 The output changes state by signals applied to one or more control inputs.

 The basic D Flip Flop has a D (data) input and a clock input and outputs Q and Q (the inverse of Q). Optionally it may also include the PR (Preset) and CLR (Clear) control inputs Diagram 3.