Learn to Design Digital Electronics with Deeds

Abstract

The purpose of this lab is to analyse a Set-Reset flip-flop schematic in the d-DcS.

To verify the behavior of the flip flop using the timing simulation,

present all the possible combinations of inputs, using a proper time scale (a suitable test sequence in the Timing Diagram window) and to explain why the circuit shows a stable auto-oscillation, and why it can not happen in the ‘real world’